1. Field of the Invention
The present invention relates to digital TV receivers, and more particularly, to a timing recovery device in a digital TV receiver which recovers a symbol clock of a received data.
2. Background of the Related Art
Recent digital TV broadcastings are made according to own transmission systems and standards of the USA, Europe, and Japan. For an example, the USA employs a VSB (Vestigial Side Band) type transmission format, an MPEG video compression format, and an AC-3 audio compression format.
For transmission of a data compressed according to above standards, synchronization signals are inserted into the data at fixed intervals, and a receiver, such as a digital TV receiver, is required to generate a clock identical to the synchronization signal used at the time of transmission for recovery of the data. A part that serves to generate such a clock at the digital TV receiver is a timing recovery part. That is, the timing recovery part reproduces a clock of a symbol stream, and a purpose of the timing recovery lies on correct and accurate prediction of a symbol transition point at the digital TV receiver based on a received data stream.
A data frame transmitted to a related art digital TV receiver will be described. As shown in FIG. 1, there are two synchronization signals used in data transmission; one is a data segment synchronization signal, and the other one is a field synchronization signal. The data segment synchronization signal, the field synchronization signal, and the data form a unit frame of 313 data segments each with 4 symbols of data segment synchronization signals, and 828 symbols of data.
The foregoing data is displayed on the digital TV receiver according to the following sequence. As shown in FIG. 2, upon reception of a broadcasting signal having the data through an antenna, a tuner 101 selects a frequency of a specific channel, and converts the frequency into an IF signal, and the IF signal is converted into a digital data through an analog/digital converting part A/D 102.
Then, the IF signal converted into the digital data is provided to a synchronization signal detecting part 103, which detects the data segment synchronization signal and the field synchronization signal inserted at the time of transmission from the digital IF signal.
For recovering the data by using the signals from the synchronization signal detecting part 103, the timing recovering part 104 recovers the timing of the synchronization signal used at the time of transmission. That is, the timing recovering part 104 recovers the timing to be applied to an A/D clock of the A/D converting part 102 by using the data segment synchronization signal.
Then, an FPLL (Frequency Phase Locked Loop) 105 demodulates the digital IF signal into a base band I signal and a base band Q signal. The Q signal is used in recovery of a carrier. Then, a channel equalizing part 106 removes errors, such as ghost, and the like, from the signal from the FPLL 105, and a video decoder 107 decodes, and displays a signal from the channel equalizing part 106 on a screen.
In a case that the timing is recovered by using the data segment synchronization signal, a phase error is erased because the timing is recovered in a state in which recovery of the carrier is not finished yet, i.e., in a state in which the phase error of the signal is present still.
Moreover, the related art timing recovering part requires a long time period for detecting the timing error because a segment synchronization section can not be known when the ghost is present. Eventually, compensation for the timing error is delayed as much, resulting in a vicious circle of failing detection of a proper data segment synchronization signal.